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[VHDL-FPGA-Verilog] sdram_vhdl

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Platform: | Size: 891904 | Author: 薛鹏展 | Hits:

[VHDL-FPGA-Verilog] Design-Of-DDR-SDRAM-Using-Verilog-HDL

Description: implementation of ddrsdram
Platform: | Size: 6144 | Author: steiner | Hits:

[Windows Develop] DDDRR_SDRAM_cD

Description: DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码）， -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
Platform: | Size: 476160 | Author: 压榨 | Hits:

[VHDL-FPGA-Verilog] DDR_check

Description: altera公司cycloneII 2c35开发测试DDR的verilog代码，带仿真波形图。-altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.
Platform: | Size: 110592 | Author: | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
Platform: | Size: 677888 | Author: 雷恒伟 | Hits:

[Other] lpddr_verilog_model

Description: 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
Platform: | Size: 39936 | Author: qiubin | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: verilog HDL语言实现在FPGA上控制DDR的逻辑，方法简单易懂，适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] ddr_kongzhiqi

Description: fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_latest.tar

Description: DDR 控制器 control verilog/vhdl 源代码 -ddr control source of verilog /vhdl
Platform: | Size: 80896 | Author: 陈成 | Hits:

[VHDL-FPGA-Verilog] micron-lpddr-sdram-lpddr_model

Description: modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。
Platform: | Size: 40960 | Author: 黄志沛 | Hits:

[VHDL-FPGA-Verilog] altera_ddr_verilog

Description: altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
Platform: | Size: 753664 | Author: 刘佳庆 | Hits:

[VHDL-FPGA-Verilog] lattice_ddr_verilog-for-orca4

Description: 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
Platform: | Size: 615424 | Author: 刘佳庆 | Hits:

[VHDL-FPGA-Verilog] mt46v16m16p_ddr

Description: 官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.
Platform: | Size: 23552 | Author: lvhenan | Hits:

[VHDL-FPGA-Verilog] DDR_sdram

Description: 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
Platform: | Size: 4935680 | Author: maxw123456789 | Hits:
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